I am a PhD candidate at Northwestern University with a B.S.
in Computer Engineering and Computer Science from Rose-Hulman
Institute of Technology.
I study compilers, specifically looking into new intermediate
representations and abstractions.
My research aims to broaden the optimization space of compilers
through intermediate representations that grant empowering degrees of freedom
through strong guarantees.
I am also interested in general static analysis, runtime system
co-design, programming languages, and memory models.
Enrico Armenio Deiana, Brian Suchy, Michael Wilkins,
Brian Homerding, Tommy McMichen, Katarzyna Dunajewski,
Peter Dinda, Nikos Hardavellas, and Simone Campanoni
International Conference on Code Generation and Optimization (CGO), 2023
Program State Element Characterization (PSEC) enables developers to more easily use modern language abstractions like OpenMP and C++ smart pointers.
To accomplish this, PSEC provides a characterization of program state elements within a given code region.
Today this process must be performed manually with no dedicated tool support.
We implement PSEC in the CARMOT tool.
Using CARMOT, developers are able to achieve parallel speedups that match those of hand-tuned OpenMP directives and avoid memory leaks with C++ smart pointers.
We hope that PSEC and CARMOT empower developers to fully utilize the rich, expanding ecosystem of modern programming language abstractions.
Angelo Matni, Enrico Armenio Deiana, Yian Su, Lukas Gross, Souradip Ghosh, Sotiris Apostolakis,
Xu, Zujun Tan, Ishita Chaturvedi, Brian Homerding, Tommy McMichen, David I. August, and
International Conference on Code Generation and Optimization (CGO), 2022
NOELLE provides abstractions to help build advanced code analyses and transformations on top of the
production quality LLVM compiler.
NOELLE has been used to accelerate a diverse set of research prototypes, with a powerful
parallelizing compiler built upon it.
It is available open source on github to help accelerate your compiler research.
Fine-Grained Acceleration using Runtime Integrated Custom Execution (RICE)
Leela Pakanati, John T. McMichen, and Zachary Estrada
International Conference on Compilers, Architectures and Synthesis for Embedded Systems
Runtime Integrated Custom Execution (RICE) relocates traditional peripheral reconfigurable
acceleration devices into the pipeline of the processor. This relocation unlocks fine-grained
acceleration previously impeded by communication overhead to a peripheral
accelerator. Preliminary simulation results on a subset of the PARSEC benchmark suite shows
promise for RICE in HPC applications. This was published in a 'work-in-progress' paper track.
Senior design project to improve the performance and efficiency of biologically-accurate neuron
simulations using the Hodgkin-Huxley model and a LUT accelerator approach. Designed and developed
novel parallel architecture to allow for parallel variable time-step integrators (VITAMIN), which
achieved strong scaling on multi-core machines. Minimized hardware area usage of LUT accelerator,
similar execution time performance. Implemented software improvements to improve execution time